Modelling of complex hardware component models in systemC/TLM

Abstract

Building SystemC/TLM-2.0 virtual prototypes requires manually transcribing register maps from Technical Reference Manuals, an error-prone bottleneck. This thesis automates it with a pipeline that turns unstructured documentation into SystemC/TLM-2.0 models via Large Language Model parsing (LLaMA 3.3 70B) and compiler-validated SystemRDL, cutting effort from hours to minutes. On three ESP32-P4 peripherals it reached 94.1–99.6% structural accuracy; full firmware compatibility additionally required manual behavioral refinement.