Digital phase detectors in VLSI

Abstract

Implementing components (Intellectual properties) compliant with indus-trial standards and implementing successful and theoretically validated algorithms is ofutmost importance. It requires, though, working on several levels of abstraction. To thatend, we propose in this Thesis two Phase Detectors; one configurable to be compliantwith the Telcordia Technologies ”Clocks for the Synchronized Network: Common GenericCriteria” and the other implementing the ”Blind Carrier Phase Tracking with Guaran-teed Global Convergence” algorithm which is published and several times referenced. Wepresent the way we have dedicated and simplified the algorithm and the normalized rulesfor VLSI implementations. We highlight the related design issues and solutions. Amongother contributions, we show how it is possible to efficiently time multiplex large multipli-ers, we present a novel Arctangent function implementation as well as a novel technique fora dynamic Accuracy adjustment of two’s complement numbers. Simulation results, FPGAimplementations as well as two International publications have backed our work proposal