Implementation of non binary LDPC decoder on FPGA for wireless communication systems

Abstract

Low Density Parity-Check (LDPC) codes have been successfully included in numerous wireless communication standards, since they achieve error correction performance very close to the Shannon limit. Non-Binary LDPC codes has better performance than the binary LDPC codes, In this thesis, we focused on the design and implementation of efficient ar-chitecture of the NB-LDPC decoder basic blocks using the Min-Max algorithm. In order to provide flexible decoder. The design and implementation of the decoder components are detailed. Various details like block schematics and simulation have been documented.