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Élément Dublin Core | Valeur | Langue |
---|---|---|
dc.contributor.author | Toumi, Said | - |
dc.contributor.other | Benalia, Nour El Houda, Directeur de thèse | - |
dc.date.accessioned | 2024-10-16T08:55:59Z | - |
dc.date.available | 2024-10-16T08:55:59Z | - |
dc.date.issued | 2024 | - |
dc.identifier.other | EP00749 | - |
dc.identifier.uri | http://repository.enp.edu.dz/jspui/handle/123456789/11020 | - |
dc.description | Mémoire de Projet de Fin d’Études : Electronique : Alger, École Nationale Polytechnique : 2024 | fr_FR |
dc.description.abstract | Deep learning networks hold immense potential in fields such as medical diagnostics, image recognition, and natural language processing. However, implementing these networks on System on Chip (SoC) platforms presents significant challenges due to the need for complex computations and substantial resources. This report presents a comprehensive investigation and performance analysis of deep learning models on various SoC platforms, focusing on hardware acceleration. Specifically, it offers a practical case study for ECG classification, providing valuable insights into the associated challenges and benefits. The project entails implementing deep learning models for ECG classification on different SoC platforms and analyzing their performance in terms of execution time, energy efficiency, and resource utilization. The findings contribute to enhancing our understanding of optimizing deep learning model performance on various SoC platforms and offer guidance for future research in this area. | fr_FR |
dc.language.iso | en | fr_FR |
dc.subject | Deep learning | fr_FR |
dc.subject | System on Chip (SoC) platforms | fr_FR |
dc.subject | ECG | fr_FR |
dc.title | Deep learning network on a SoC platform : implementation and analysis | fr_FR |
dc.type | Thesis | fr_FR |
Collection(s) : | Département Electronique |
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Fichier | Description | Taille | Format | |
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pfe.2024.eln.TOUMI.Said..pdf | PN00724 | 457.48 kB | Adobe PDF | Voir/Ouvrir |
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